Luận án Giải pháp chuyển đổi dấu phẩy tĩnh và hiệu chỉnh sai lệch trong TI-ADC cho khối thu băng rộng

Nội dung text: Luận án Giải pháp chuyển đổi dấu phẩy tĩnh và hiệu chỉnh sai lệch trong TI-ADC cho khối thu băng rộng

1. 119 KẾT LUẬN Trên cơ sở đặc điểm của TI-ADC áp dụng trong khối thu băng rộng, Luận án đưa ra những phân tích về kỹ thuật hiệu chỉnh đồng thời lệch hệ số khuếch đại và thời gian lấy mẫu của TI-ADC theo nguyên tắc lọc thích nghi loại bỏ nhiễu. Việc hiệu chỉnh đồng thời hai loại sai lệch này giúp cải thiện hiệu năng của TI-ADC và giảm bớt độ phức tạp của mạch thiết kế. Bên cạnh đó, Luận án phát triển giải pháp FFC có nhóm tín hiệu nhằm giảm thời gian thực hiện FFC. Giải pháp này được áp dụng cho các thuật toán DSP, bao gồm FFT đa phương thức trong các thiết bị WLAN chuẩn IEEE 802.11ax và bộ hiệu chỉnh TI-ADC ANC. Các giải pháp đề xuất đã trải qua quá trình mô phỏng và được thực nghiệm trên các thiết bị phần cứng, tổng hợp bằng công cụ Cadence, công cụ Genus 162, PDK XFab SOI CMOS 180nm, từ đó chứng minh tính hiệu quả trên thực tế. A. Một số kết quả đạt được của Luận án 1. Đề xuất giải pháp hiệu chỉnh đồng thời lệch hệ số khuếch đại, thời gian lấy mẫu của TI-ADC dựa trên nguyên tắc lọc thích nghi loại bỏ nhiễu. Kỹ thuật này cho phép ứng dụng rộng rãi cho các bộ TI-ADC tốc độ cao trong khối thu băng rộng. 2. Đề xuất FFC có nhóm tín hiệu và chứng minh tính hiệu quả của đề xuất. Giải pháp nhóm tín hiệu trong FFC đưa ra dựa trên việc chứng minh cơ sở toán học của việc nhóm dữ liệu dựa trên dải biên độ tín hiệu vào, ra và hàm truyền đạt của các khối chức năng trong hệ thống DSP. Giải pháp đề xuất nhằm cải thiện thời gian chuyển đổi FFC, tối ưu tài nguyên phần cứng và tích hợp các thiết kế thuật toán hiệu chỉnh vào lõi ADC đáp ứng yêu cầu các máy thu băng rộng.
2. 121 lệch băng thông theo nguyên tắc ANC. - Nghiên cứu áp dụng bộ hiệu chỉnh TI-ADC-ANC kết hợp cùng FFT đa phương thức đã thiết kế để xây dựng các bộ thu trong thiết bị WLAN băng rộng, tốc độ cao.
3. 123 actions on Fundamentals, Vol.E105-A,No.12,pp.-,Dec. 2022.(Đã được chấp nhận đăng) II. CÁC CÔNG TRÌNH CÓ LIÊN QUAN ĐẾN LUẬN ÁN [J4] Loan Pham-Nguyen, Nguyen Thien Viet, Dinh Thi Kim Phuong , “A Configurable Direct Delta-Sigma Converter for Frequency Division Duplex (FDD) Bands from 0.4 GHz to 3.6 GHz”, Journal of Science and Technology Technical Universities, pp: 067–075, Volume 32, Issue 1, Jan, 2022.
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12. PL2 15 15 X X nk X(k) = (n4 + 16n3).W256 (A.4) n4=0 n3=0 Công thức (A.1) khai triển tính FFT 2048 điểm sử dụng 5 tầng trong đó các Butterfly có Radix tương ứng như Bảng A.1. Để chứng minh các giá trị n, k của bảng 3.2,lần lượt phân tích từng tầng như sau: Tầng số 2, tầng số 3: Xét tầng số 2, do chỉ sử dụng radix 2 nên n1 nhận giá trị 0 hoặc 1, thay vào công thức (A.2) có công thức (A.5) 15 15 1 X X X (n4+16n3+256n2)(k1+2k2+4k3+64k4) X(k) = [x(n4 + 16n3 + 256n2) × W1024 n4=0 n3=0 n2=0 (A.5) (n4+16n3+256n2+512)(k1+2k2+4k3+64k4) +x(n4 + 16n3 + 256n2 + 512) × W1024 ] 15 15 1 X X X X(k) = [x(n4 + 16n3 + 256n2) + x(n4 + 16n3 + 256n2 + 512) (A.6) n4=0 n3=0 n2=0 512.(k1+2k2+4k3+64k4) (n4+16n3+256n2)(k1+2k2+4k3+64k4) ×W1024 ] × W1024 N2 1 k.N Do tính chất đối xứng của Tw, WN = W2 ; WN = 1 ta có : 15 15 1 X X X X(k) = [x(n4 + 16n3 + 256n2) + x(n4 + 16n3 + 256n2 + 512) n4=0 n3=0 n2=0 (A.7) 512k1 5122k2 2.1024k3 32.1024k4) (n4+16n3+256n2)(k1+2k2+4k3+64k4) ×W1024 × W1024 × W1024 × W1024 ] × W1024 15 15 1 X X X  k1  X(k) = x(n4 + 16n3 + 256n2) + x(n4 + 16n3 + 256n2 + 512).W2 n4=0 n3=0 n2=0 (A.8) (n4+16n3+256n2)(k1+2k2+4k3+64k4) ×W1024
13. PL4 G4(δ1 + 2δ2 + 4δ3 + 8δ4, n4) = (A.16) 1 1 1 1 X X X X X3 [n4 + 16(8σ1 + 4σ2 + 2σ3 + σ4) + 256k2 + 512k1] σ1=0 σ2=0 σ3=0 σ4=0 (8σ1+4σ2+2σ3+σ4)(δ1+2δ2+4δ3+8δ4) ×W16 Khai triển công thức (A.16) thu được công thức (A.17). G4(δ1 + 2δ2 + 4δ3 + 8δ4, n4) = (A.17) 1 1 1 1 X X X X σ1δ1 σ2δ1 [ [ ( X3 [n4 + 16(8σ1 + 4σ2 + 2σ3 + σ4) + 256k2 + 512k1] × W2 .(−j) ) σ1=0 σ2=0 σ3=0 σ4=0 σ2δ2 (δ1+2δ2)(2σ3+σ4) σ3δ3 σ4δ3 σ4δ4 ×W2 .W16 ] × W2 .(−j) ].W2 Đặt: X4 [n4 + 16(8σ1 + 4σ2 + 2σ3 + σ4) + 256k2 + 512k1] = (A.18) (δ1+2δ2+4δ3+8δ4) G4(δ1 + 2δ2 + 4δ3 + 8δ4, n4) × W256 Công thức (A.19) là công thức thực hiện FFT cho tầng số 4. 15 X n4.k4 X(k) = X4 [n4 + 16(8σ1 + 4σ2 + 2σ3 + σ4) + 256k2 + 512k1] × W16 (A.19) n4=0 4 Tầng số 5: Ở tầng số 5 sử dụng các butterfly Radix 2 , Với n4, k4 như sau: n4 = 8α1 +4α2 +2α3 +α4 và k4 = β1 +2β2 +4β3 +8β4 và α1,2,3,4 = 0, 1 ; β1,2,3,4 = 0, 1. Thay các giá trị n4, k4 vào công thức (A.19) có công thức (A.20). Công thức này là công thức thực hiện FFT đa phương thức tại tầng số 5. 1 1 1 1 X X X X X(k) = [ ( [ X4(8α1 + 4α2 + 2α3 + α4 + 16(8σ1 + 4σ + 2σ3 + σ4) α1=0 α2=0 α3=0 α4=0 (A.20) β1.α1 β1α2 β1.α2 (2α3+α4)(β1+2β2 β3α4 β4α4 +256k2 + 512k1).W2 .(−j) ].W2 W16 ).2 ].W2
14. PL6 orig_snr = zeros(n_sims,n_fins); orig_sndr = zeros(n_sims,n_fins); cal_sfdr = zeros(n_sims,n_fins); cal_snr = zeros(n_sims,n_fins); cal_sndr = zeros(n_sims,n_fins); %% Randomize the mismatches g_mis = sigma_g * randn(n_sims,n_channels); s_mis = sigma_t * randn(n_sims,n_channels); o_mis = sigma_0 * randn(n_sims,n_channels); %% Kaiser window to estimate PSD kaiser_win=kaiser(n_samples,38); kaiser_win_rbw=enbw(kaiser_win,fs); %% Randomize the errors noise_mat = (sigma_jitt + sigma_noise) * randn(n_sims,Nfft); %% Monte Carlo tic % Preallocate signals out_tiadc = zeros(1,Nfft); out_ideal = zeros(1,Nfft); t = 0:Ts:0+Ts*(Nfft-1); assignin(’base’,’t’, t); assignin(’base’,’t_s’, t); for sim_i=1:n_sims % Set errors and noise gain_err = g_mis(sim_i,:); skew_err = s_mis(sim_i,:); offset_err = o_mis(sim_i,:); noise = noise_mat(sim_i,:); for fin_i=1:n_fins assignin(’base’,’nyquist_zone’, NZs(fin_i)); assignin(’base’,’NY’, NZs(fin_i)); % Assign the bin to input
15. PL8 %[orig_snr1(sim_i,fin_i), orig_sndr1(sim_i,fin_i), orig_sfdr1(sim_i,fin_i)] = myperfMeasureTung(out_tiadc,fin_bin,n_channels); %[cal_snr1(sim_i,fin_i), cal_sndr1(sim_i,fin_i), cal_sfdr1(sim_i,fin_i)] = myperfMeasureTung(comp_sig,fin_bin,n_channels); % Original performance [orig_spec F]=periodogram(out_tiadc,kaiser_win,numel(out_tiadc),fs,’power’); try orig_snr(sim_i,fin_i) = snr(orig_spec,F,kaiser_win_rbw,’power’); catch err orig_snr(sim_i,fin_i) = snr(orig); end try orig_sfdr(sim_i,fin_i)=sfdr(orig_spec,F,’power’); catch err orig_sfdr(sim_i,fin_i)=sfdr(orig); end try orig_sndr(sim_i,fin_i)=sinad(orig_spec,F,kaiser_win_rbw,’power’); catch err orig_sndr(sim_i,fin_i)=sinad(orig); end % Calibrated performance if not(isnan(comp_sig(:))) % Performance [cal_specF]= periodogram(comp_sig(:),kaiser_win,numel(comp_sig(:)),fs,’power’); try
16. PL10 max_tmp = max(eval([’sig_log’ num2str(grp_i)])); block_attrs(grp_i).OutMax=max(block_attrs(grp_i).OutMax,max_tmp); end end end end end toc %% Store the result result_file=[input_file’.multisim_’ num2str(n_sims)’.res.mat’]; save(result_file, ’fins’, ’orig_sfdr’,’orig_snr’,’orig_sndr’, ’cal_sfdr’,’cal_snr’,’cal_sndr’, ’g_mis’,’s_mis’,’o_mis’,’noise_mat’); if (n_block_grps>0) save(result_file,’block_attrs’,’-append’); end save_system(mdl); close_system(mdl); B.2. Hàm tạo mô hình sim_log % Create log system by adding Toworkspace blocks after interested blocks to log signal max, min values. Input: system, dut: system and dut. file [system’_block_tags.mat’] contains variable block_tags. Output: file [system’_log’] is new model in which new ToWorkspace blocks are added. function newsystem = create_log_model(system, dut, block_tags_file) load_system(system); newsystem=[system’_log’];
17. PL12 if (n_block_grps<block_tags(blk_i).tag) n_block_grps=block_tags(blk_i).tag;end end end % Blocks that be observed/logged max/min values, configure wordlength are grouped block_attrs=struct(’name’,{},’OutMin’,{},’OutMax’,{},’range’,{}, ’OutDataTypeStr’,{},’ProductDataTypeStr’,{},’CoefDataTypeStr’,{},’RndMeth’,{},’ ’,{}); %% Find the groups and add ToWorkspace block to log values for grp_i=1:n_block_grps block_names=find_system([newsystem ’/’ dut],’LookUnderMasks’,’all’,’tag’,num2str(grp_i)); block_attrs(grp_i).name=block_names; block_id=get_param(char(block_names(1)),’Handle’); block_parent=get_param(block_id,’Parent’); block_ports=get_param(block_id,’PortHandles’); block_pos=get_param(block_id,’Position’); % for each group, add min,max blocks to log the max, min of the block outputs log=add_block(’built-in/ToWorkspace’,[char(block_parent) ’/log’ num2str(grp_i)]); set_param(log,’VariableName’,[’sig_log’ num2str(grp_i)]); set_param(log,’MaxDataPoints’,[’inf’]); set_param(log,’SampleTime’,’-1’); set_param(log,’Position’,[block_pos(1)+50 block_pos(2)-20 block_pos(1)+90 block_pos(2)]); log_ports=get_param(log,’PortHandles’); add_line(block_parent,block_ports.Outport,log_ports.Inport); end save([newsystem ’_block_attrs.mat’],’block_attrs’); save([newsystem ’_block_tags.mat’], ’block_tags’); save_system(newsystem);